Fault-tolerant Method and Simulation of Heterogeneous Multi-core Processor Based on Speculative Mechanism

Authors

Shigan Yu, 1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; ;2. School of Computer and Control Engineering, University of Chinese Academy of Sciences, Beijing 100049, China; ;3.National Engineering Laboratory for Advanced Processor Technology, Chengdu 610218, China; ;4.Information Engineering college, Fuyang Normal University, Fuyang 236041, China;
Zhimin Tang, 1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; ;2. School of Computer and Control Engineering, University of Chinese Academy of Sciences, Beijing 100049, China; ;3.National Engineering Laboratory for Advanced Processor Technology, Chengdu 610218, China; ;
Xiaochun Ye, 1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; ;2. School of Computer and Control Engineering, University of Chinese Academy of Sciences, Beijing 100049, China; ;
Dongrui Fan, 1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; ;2. School of Computer and Control Engineering, University of Chinese Academy of Sciences, Beijing 100049, China; ;

Abstract

Abstract: Heterogeneous multicore is one of the important branches of processors,but they are still faced with frequent transient failures. TMR(Triple mode redundancy) is the main method to solve transient faults, which has the characteristics of low efficiency and high power consumption, a high-performance Fault-Tolerant Scheduling Algorithm with Speculative mechanism(FTSAS) is proposed. Each heterogeneous core can execute tasks independently, the state values of the first completed core are recorded, and the first completed core continues to perform the next task with forward speculative method. The results are compared by backward core, the majority consensus principle is adopted to ensure the reliability of the system. The simulation results show the average performance of the FTSAS is improved by 12.9% compared with state-of-the-art methods. When 200 errors are injected, the FTSAS has a similar fault-tolerant effect, however, FTSAS can achieve 11.4% average efficiency improvement and 15.8% average power consumption decrement.

Recommended Citation

Yu, Shigan; Tang, Zhimin; Ye, Xiaochun; and Fan, Dongrui (2019) "Fault-tolerant Method and Simulation of Heterogeneous Multi-core Processor Based on Speculative Mechanism," Journal of System Simulation: Vol. 31: Iss. 12, Article 16.
DOI: 10.16182/j.issn1004731x.joss.19-FZ0346
Available at: https://dc-china-simulation.researchcommons.org/journal/vol31/iss12/16

First Page

2685

Revised Date

2019-07-19

DOI Link

https://doi.org/10.16182/j.issn1004731x.joss.19-FZ0346

Last Page

2695

CLC

TP391.7

Recommended Citation

Yu Shigan, Tang Zhimin, Ye Xiaochun, Fan Dongrui. Fault-tolerant Method and Simulation of Heterogeneous Multi-core Processor Based on Speculative Mechanism[J]. Journal of System Simulation, 2019, 31(12): 2685-2695.

DOI

10.16182/j.issn1004731x.joss.19-FZ0346